A CPU chip (Central Processing Unit chip: arithmetic processing apparatus) in recent years includes a plurality of CPU cores (arithmetic processing units), in which the plurality of CPU cores execute user program instructions in parallel to increase an arithmetic speed. Further, there has been proposed a CPU chip of a heterogeneous configuration in which a plurality of general-purpose CPU cores executing user program instructions are mixed with a plurality of OS-dedicated CPU core executing instructions of an OS (Operating System), that is, basic software. In the above CPU chip, the plurality of general-purpose CPU cores process a complicated calculation instruction of the user program to enhance calculation processing efficiency, and the OS-dedicated CPU core executes interruption processing and a memory access associated with data copy in the OS, so as to prevent a useless processing delay and a disturbance in the parallel calculation processing by the general-purpose CPU cores.
The CPU chip is disclosed in, for example, Japanese Laid-open Patent Publication No. 2009-15509, Japanese Laid-open Patent Publication No. 10-254775, Japanese Laid-open Patent Publication No. 2008-114065, Japanese Laid-open Patent Publication No. 2010-140146, and Japanese Laid-open Patent Publication No. 2011-070654.
In such a multi-core CPU chip of a heterogeneous configuration, memory access bands are separately provided for the general-purpose CPU cores that execute calculation processing and the OS-dedicated CPU core, so that processing does not influence each other. Typically, at the stage of designing the CPU chips, each cache memory is separately allocated for the general-purpose CPU cores and the OS-dedicated CPU core, to optimize the memory access bands for the general-purpose CPU cores and the OS-dedicated CPU core according to the capacity of the cache memory.
However, the optimal frequencies of memory access requests produced by the OS-dedicated CPU core are variously different according to use states, and therefore, it is difficult to optimize an amount of resources for a memory access by the OS-dedicated CPU core, at the design stage of the CPU chip. Although preferential execution is needed for the memory access from the OS-dedicated CPU core, which is important because of relating to interruption processing etc., if a memory access band from the OS-dedicated CPU core is designed to be too wide, congestion may occur in memory accesses in calculation processing by the general-purpose CPU cores, which may disable to increase memory access efficiency in the overall multi-CPU cores.